For single crystal semiconductor materials, all lattice directions and lattice planes in a unit cell of a single crystal material can be described by a mathematical description known as a Miller Index. On one hand, the notation [hkl] in the Miller Index defines a crystal direction or orientation, such as the [001], [100], [010], [110], and [111] directions in a cubic unit cell of single crystal silicon. On the other hand, the crystal planes or facets of a single crystal silicon unit cell are defined by the notation (hkl) in Miller Index, which refers to a particular crystal plane or facet that is perpendicular to the [hkl] direction. For example, the crystal planes (100), (110), and (111) of the single crystal silicon unit cells are respectively perpendicular to the [100], [110], and [111] directions. Additional, because the unit cells are periodic in a semiconductor crystal, there exist families or sets of equivalent crystal directions and planes. The notation <hkl> in the Miller Index therefore defines a family or set of equivalent crystal directions or orientations. For example, the <100> directions include the equivalent crystal directions of [100], [010], and [001]; the <110> directions include the equivalent crystal directions of [110], [011], [101], [-1-10], [0-1-1], [-10-1], [-110], [0-11], [-101], [1-10], [01-1], and [10-1]; and the <111> directions include the equivalent crystal directions of [111], [-111], [1-11], and [1]-[1]. Similarly, the notation (hkl) defines a family or set of equivalent crystal planes or facets that are respectively perpendicular to the <hkl> directions. For example, the {100} planes include the set of equivalent crystal planes that are respectively perpendicular to the <100> directions.
In present semiconductor technology, CMOS devices, such as n-FETs and p-FETs, are typically fabricated on semiconductor wafers that have a single crystal direction. In particular, most of today's semiconductor devices are built upon Si substrates oriented along the {100} planes of Si.
Electrons are known to have a high mobility on the {100} planes of Si, but holes are known to have a high mobility on the {110} planes of Si. On one hand, hole mobility values on the {100} surfaces of Si are approximately 2 times lower than the hole mobility values on the {110} surfaces of Si. Therefore, p-FETs formed on a {110} Si surface will exhibit significantly higher drive currents than p-FETs formed on a {100} Si surface. On the other hand, electron mobility values on the {110} surfaces of Si are significantly degraded in comparison with the {100} Si surfaces. Therefore, the {100} Si surfaces are more optimal for forming n-FETs.
Methods for forming planar substrates with different device regions of different surface crystal orientations, which are commonly referred to as the hybrid orientation technology (HOT), have been previously described by, for example, U.S. Patent Application Publications No. 2005/0093104 and 2005/0256700.
FIGS. 1A-1F illustrate processing steps typically used for forming CMOS devices with the HOT substrates. Specifically, FIG. 1A shows a semiconductor-on-insulator (SOI) structure that comprises a base semiconductor substrate layer 112 having a first surface crystal orientation, a buried insulator layer 114, and a semiconductor device layer 116 having a second, different surface crystal orientation. A dielectric hard mask layer 118 is deposited over the SOI substrate.
The dielectric hard mask layer 118 is subsequently patterned and then used for selectively removing portions of the underlying semiconductor device layer 16 and the insulator layer 114, thereby resulting in a trench 120 that extends through layers 116 and 114 and exposes an upper surface of the base semiconductor substrate layer 12. Dielectric spacers 122 are then formed over sidewalls of the trench 120, as shown in FIG. 1B.
Next, a selective epitaxial growth step is carried out to grow a semiconductor structure 124 on the exposed upper surface of the base semiconductor substrate layer 112, as shown in FIG. 1C. Because the dielectric spacers 122 cover the semiconductor device layer 116 on the sidewalls of the trench 120, semiconductor nucleation cannot occur on such trench sidewalls, and the selective epitaxial growth therefore can only proceed from the upper surface of the base semiconductor substrate layer 112 at the bottom of the trench 120. Correspondingly, the resulting semiconductor structure 124 has the same surface crystal orientation as the base semiconductor substrate layer 112 (i.e., the first surface crystal orientation), instead of the semiconductor device layer 116. After planarizing the entire structure to remove an over-growing portion of the semiconductor structure 124 and the entire dielectric hard mask layer 118, isolation regions 126 are formed in the substrate to define a first device region, which has a SOI structure including the semiconductor device layer 116 and the buried insulator layer 114 on the base semiconductor substrate layer 112, and a second device region, which has a bulk semiconductor structure including the epitaxially grown semiconductor structure 124 on the base semiconductor substrate layer 112, as shown in FIG. 1D. The resulting substrate is therefore a hybrid orientation substrate, because the first and second device regions have different surface crystal orientations, i.e., the semiconductor device layer 116 at the first device region has second, different crystal orientation while the epitaxially grown semiconductor structure 124 at the second device region has the first crystal orientation.
Subsequently, complementary transistors can be respectively formed at the first and second device regions of such a hybrid orientation substrate. For example, an n-FET comprising a source region (NS), a drain region (ND), and a gate conductor (NG) can be formed at the first device region, and a p-FET comprising a source region (PS), a drain region (PD), and a gate conductor (PG) can be formed at the second device region, as shown in FIG. 1E.
However, the first and second device regions of the hybrid orientation substrate are isolated from each other by the dielectric spacer 122, as shown in FIGS. 1D-1E. In order to electrically connect the n-FET and p-FET devices, a conductive connector 128 must be provided over the hybrid orientation substrate above the dielectric spacer 122, as shown in FIG. 1F, which requires additional processing steps and adds to the manufacturing costs of the n-FET and p-FET devices. Further, the conductive connector 128 protrudes above the substrate surface and further increases the contact resistances of the n-FET and p-FET devices.
There is a continuing need for improved CMOS device structures that can be fabricated by simplified processes at reduced costs.